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Keynote Speech Sessions
Keynote Session K1
Hall 405, 4th Floor, Nanjing Platinum Hanjue Hotel
9:00-10:30, Oct.26, 2022, Wednesday
K1-1 What Are 2D Materials Good For?
Speaker：Prof. Eric Pop，Stanford University，USA
Bio: Eric Pop is a Professor of Electrical Engineering (EE) and Materials Science & Engineering (by courtesy) at Stanford. He was previously on the faculty of UIUC (2007-13) and worked at Intel (2005-07). His research interests are at the intersection of electronics, nanomaterials, and energy. He received his PhD in EE from Stanford and three degrees from MIT (MEng and BS in EE, BS in Physics). His honors include the Presidential Early Career Award (PECASE), Young Investigator Awards from the Navy, Air Force, NSF and DARPA, and several best paper and best poster awards with his students. In 2018, he was named one of the world’s Highly Cited Researchers by Web of Science. He is an IEEE Fellow, an Editor of 2D Materials, has served as General Chair of the Device Research Conference, and on program committees of VLSI, IEDM, APS, and MRS. In his spare time he tries to avoid injuries while snowboarding and in a past life he was a DJ at KZSU 90.1 FM, from 2000-04. Additional information about the Pop Lab is available online at http://poplab.stanford.edu
Abstract：This talk will present my (admittedly biased) perspective of what two-dimensional (2D) materials could be good for. For example, they may be good for applications where their ultrathin nature and lack of dangling bonds give them distinct advantages, such as flexible electronics  or DNA-sorting nanopores . They may not be good for applications where conventional materials work well, like in transistors thicker than a few nanometers. I will focus on the case of 2D materials for 3D heterogeneous integration of electronics, which presents significant advantages for energy-efficient computing . In this context, 2D materials could be monolayer transistors with ultralow leakage  (taking advantage of larger band gaps than silicon), used as access devices for high-density data storage . For example, recent results from our group have shown monolayer transistors with record performance [6,7], which cannot be achieved with sub-nanometer thin conventional semiconductors. I will also describe some less conventional applications, using 2D materials as highly efficient thermal insulators  and as thermal transistors . These could enable control of heat in “thermal circuits” analogous with electrical circuits. Combined, these studies reveal fundamental limits and some unusual applications of 2D materials, which take advantage of their unique properties.
K1-2 The integration of Industry and Education Supports Interdisciplinary Achievements
Speaker: Prof. Hanming Wu, Zhejiang University, China
Bio：Dr. Wu received his PhD degree from the institute of mechanics, Chinese Academy of Sciences in 1987 and was promoted to Research Professor at the same institute in 1989. Subsequently, he conducted post doctoral research at UT-Austin and UC-Berkeley. He also has extensive R&D experiences in the US semiconductor industry, first at Novellus and then at Intel until 2000. He joined SMIC in 2001 and was instrumental in setting up R&D team for etch process. As a leader on the national project《65-45-32nm Process Technology Development》, he initiated the national 65-32nm CMOS pre-manufacture projects. As VP of SMIC’s R&D, Dr. Wu played a key role in SMIC’s path finding activities during 2012-2015. He had published more than 100 papers and is the inventor on more than 80 granted patents on semiconductor processes. In 2019, he joined Zhejiang University as a professor.
He has earned three National 2nd Level Awards for Advanced Technology Achievement. He was elected as “2014 The Top Ten National Excellent Scientists” and “2014 National Outstanding Talent of Specialty”. He was also selected to be “Beijing Scholar” in 2013.
He was elected as an academician of Chinese Academy of Engineering in 2019.
Abstract： In the present talk, the discussion for the integration of industry and education system is conducted. The main challenge is the confliction between traditional teaching system and emerging interdisciplinary, especially for process science and technology. The iconic technology of the IC industry should be a completed process flow. There are three main challenges in a complete process science and technologies: fundamental patterning, new material process and yield enhancement. The collaboration among industry, education and research is essential for future technology development. The research achievement can be transferred to industry only through pilot-test line. Therefor it is very important to construct a pilot test line so that interdisciplinary can be integrated and many research achievements can be industrialized. Resent chip manufacture capability shortage indicates that capacity expanding should be encouraged to meet market demands in China as well as all around world.
In summary, IC technology development in China should be very challenge. There might be some opportunities to technology followers in Post-Moore era. In the future, it is helpful to promote our IC R&D culture toward application and industry.
Keynote Session K2
Hall 405, 4th Floor, Nanjing Platinum Hanjue Hotel
10:45-12:15, Oct.26, 2022, Wednesday
K2-1 Toward 6G: From New Hardware Design to Wireless Semantic and Goal-Oriented Communication Paradigms
Speaker： Emilio Calvanese Strinati, CEA Leti, France
Bio：Dr. Emilio Calvanese Strinati obtained his Engineering Master degree in 2001 from the University of Rome ‘La Sapienza’ and his Ph.D in Engineering Science in 2005. He then started working at Motorola Labs in Paris in 2002. Then in 2006 he joint CEA/LETI as a research engineer. From 2007, he becomes a PhD supervisor. From 2010 to 2012, Dr. Calvanese Strinati has been the co-chair of the wireless working group in GreenTouch Initiative which deals with design of future energy efficient communication networks. From 2011 to 2016 he was the Smart Devices & Telecommunications European collaborative strategic programs Director. Between December 2016 and January 2020 is was the Smart Devices & Telecommunications Scientific and Innovation Director. Since February 2020 he is the Nanotechnologies and Wireless for 6G (New-6G) Program Director focusing on future 6G technologies. In December 2013 he has been elected as one of the five representative of academia and research center in the Net!Works 5G PPP ETP. From 2017 to 2018 he was one of the three moderators of the 5G future network expert group. Between 2016 and 2018 he was the coordinator of the H2020 joint Europe and South Korea 5GCHAMPION project that showcased at the 2018 winter Olympic Games, 5G technologies in realistic operational environments. Since July 2018 he is the coordinator of the H2020 joint Europe and South Korea 5G-AllStar project. Since 2018 he holds the French Research Director Habilitation (HDR). In 2021 he started the coordination of the H2020 European project RISE-6G, focusing on the design and operation of Reconfigurable Intelligent Surfaces in future high frequency 6G networks. Since February 2021 he is also the director of the New-6G (Nano Electronic & Wireless for 6G) initiative , dedicated to the required convergence between microelectronic & telecom, hardware & software, network & equipment for upcoming 6G technologies.
E. Calvanese Strinati has published around 150 papers in international conferences, journals and books chapters, given more than 200 international invited talks, keynotes and tutorials. He is the main inventor or co-inventor of more than 75 patents. He has organized more than 100 international conferences, workshops, panels and special sessions on green communications, heterogeneous networks and cloud computing hosted in international conferences as IEEE GLOBCOM, IEEE PIMRC, IEEE WCNC, IEEE ICC, IEEE VTC, EuCnC, IFIP, EUCNC and European Wireless. He is the general chair of EUCNC & 6G Summit 2022.
K2-2 The Ecological Outcome of Pursuing Efficiency in ICT
Speaker： Prof. David BOL, ECS group, ICTEAM Institute, UCLouvain, Belgium
Bio：David Bol is an Associate Professor at UCLouvain. He received the Ph.D degree in Engineering Science from UCLouvain in 2008 in the field of ultra-low power digital nanoelectronics. In 2005, he was a visiting Ph.D student at the CNM, Sevilla, and in 2009, a postdoctoral researcher at intoPIX, Louvain-la-Neuve. In 2010, he was a visiting postdoctoral researcher at the UC Berkeley Lab for Manufacturing and Sustainability, Berkeley. In 2015, he participated to the creation of e-peas semiconductors spin-off company. Prof. Bol leads the Electronic Circuits and Systems (ECS) group focused on ultra-low-power design of integrated circuits for environmental and biomedical IoT applications including computing, power management, sensing and wireless communications. He is actively engaged in a social-ecological transition in the field of ICT research with a post-growth approach. Prof. Bol has authored more than 150 papers and conference contributions and holds three delivered patents. He (co-)received four Best Paper/Poster/Design Awards in IEEE conferences (ICCD 2008, SOI Conf. 2008, FTFC 2014, ISCAS 2020) and supervised the PhD thesis of Charlotte Frenkel who received the 2021 Nokia Bell Scientific Award and the 2021 IBM Innovation Award for her PhD. He serves as a reviewer for various IEEE journals and conferences and presented several keynotes in international conferences. On the private side, Prof. Bol pioneered the parental leave for male professors in his faculty, to spend time connecting to nature with his family.
Abstract：Over the 20th century, technological progress enabled a strong economic growth, the improvement of living standards and life expectancy. This technological progress relied on a growing exploitation of energy sources that led to the Anthropocene where humanity is threatened by several ecological disasters including climate change and biodiversity collapse. Information and communication technologies (ICT) based on electronic circuits and systems are no exception as they contribute to climate change with annual greenhouse gas (GHG) emissions above 1000 MTCO2e, which accounts for 2-4% of the global carbon footprint.
In ICT, research and technology development often focus on increasing efficiency metrics. Empirical laws such as Moore’s law capture the exponential increase of this efficiency by planning the growth of a Key Performance Indicators (KPIs), e.g. the number of transistors, at the fixed usage of a physical resource, e.g. a silicon wafer. Despite this efficiency improvement, the environmental footprint of ICT is not decreasing over time. In this keynote, we will discuss the ecological outcome of pursuing efficiency in the current global socio-technical context targeting economic growth, on the basis of recent UCLouvain research on the evolution of the environmental footprint of semiconductor manufacturing, mobile Internet access and datacenter usage. We will question the possibility of decoupling the growth in the global technology usage (i.e. the number of transistors produced per year worldwide) from the physical resource usage (total number of wafers produced per year) and the associated GHG emissions of the ICT sector.
We argue that an absolute decoupling is not possible with the current business model in ICT research and innovation, which rely on the quest for efficiency and the growth of the technology usage. As a result, researchers, innovators and business developers have the duty to change course to contribute to the fight against ecological disasters rather than to their severity. This requires considering sobriety in ICT research and innovation for rethinking our socio-economic models and innovation roadmaps.
Keynote Session K3
Hall 405, 4th Floor, Nanjing Platinum Hanjue Hotel
8:30-10:00, Oct.27, 2022, Thursday
K3-1 EUV Lithography: What's Now and What's Next
Speaker：Dr. Anthony Yan, ASML
Bio：Anthony Yen is Vice President and Head of Technology Development Center at ASML, responsible for providing the company with mid- and long-term technology directions and working with customers, peers, universities, and research centers to develop enabling technologies. Prior to joining ASML, he headed Nanopatterning Technology Infrastructure Division at TSMC and played a key role in developing EUV lithography for high-volume production. He received his undergraduate degree in electrical engineering from Purdue University and his master’s, engineer’s, doctoral, and MBA degrees from MIT. He is a Fellow of the IEEE and SPIE, and was awarded Outstanding Electrical and Computer Engineer by Purdue.
Speaker：Prof. Kea-Tiong (Samuel) Tang ，Tsing Hua Univ., Taiwan, China
Bio：Dr. Kea-Tiong (Samuel) Tang received the B.S. degree in electrical engineering from National Taiwan University, Taipei, Taiwan in 1996, and received the M.S. and Ph.D. degrees in electrical engineering from California Institute of Technology, Pasadena, CA, USA, in 1998 and 2001, respectively. During 2001-2006, he was a Senior Electrical Engineer with Second Sight Medical Products, Inc., Sylmar, CA, USA, designing mixed signal ASIC for retina prosthetic device. Since 2006, he has joined the Electrical Engineering Faculty at National Tsing Hua University, Hsinchu, Taiwan, and is currently Professor. Dr. Tang currently serves as the Editor-in-Chief of IEEE Transactions on Biomedical Circuits and Systems, the Vice President of Regional Activities and Membership of IEEE Circuits and Systems Society, and the Chair of IEEE Taipei Section. His research interests include neuromorphic SoC design, Energy efficient AI accelerator, bio/chemical sensing system, analog and mixed signal IC design, and biomedical SoC design.
Abstract：To efficiently executing algorithms and software, developing low-power and low-latency hardware have become top priority for TinyML applications. To achieve this goal, data processing techniques in sensor and memory utilizing the array structure have drawn much attention. In-sensor computing serves to reduce data transfer; In-memory computing is efficient to reduce memory access and intermediate data movement. In this talk, recent progresses, advantages, and challenges of In-sensor and In-memory computing from system point-of-view will be discussed.
Keynote Session K4
Hall 405, 4th Floor, Nanjing Platinum Hanjue Hotel
10:30-12:00, Oct.27, 2022, Thursday
K4-1 Recent Progress in R&D Activities on SiC Power Devices and Its Social Implementation
Speaker：Dr. Yasunori Tanaka，National Institute of Advanced Industrial Science and Technology (AIST), Japan
Bio：Dr. Yasunori Tanaka is Deputy Director of ADvanced Power Electronics Research Center (ADPERC) in National Institute of Advanced Industrial Science and Technology (AIST). He received the PhD degree from the Osaka University in 1996 in the research field of the surface science on semiconductors. In the same year, he joined the Electrotechnical Laboratory (ETL) and started his R&D activities on the device process of the semiconductor devices. After the integration of ETL’s activities into AIST in 2001, he was involved the design and development of SiC power devices, such as PiN diodes and FETs. From 2014 to 2016, he joined in the Cabinet Office, Government of Japan, to promote the national project (SIP: Strategic Innovation Program) of next generation power electronics technologies. After returning to AIST in 2016, he has managed the several national projects on R&D of SiC power devices up to now.
K4-2 FD-SOI Technology and Design Techniques for IoT Applications – The Exciting New Life of Analog/RF Designers with Body Biasing Techniques
Speaker: Dr. Andreia Cathelin ，ST Microelectronics, France
Bio：Andreia Cathelin (M’04, SM’11) started electrical engineering studies at the Polytechnic Institute of Bucarest, Romania and graduated with MS from the Institut Supérieur d’Electronique du Nord (ISEN), Lille, France in 1994. In 1998 and 2013 respectively, she received PhD and “habilitation à diriger des recherches” (French highest academic degree) from the Université de Lille 1, France. Since 1998, she has been with STMicroelectronics, Crolles, France, now Technology R&D Fellow. Her focus areas are in the design of RF/mmW/THz and ultra-low-power circuits and systems. She is leading and driving research in advanced topics inside the company R&D program and through leadership cooperation with major universities around the world. Andreia is very active in the IEEE community since more than 15 years, strongly implied with SSCS and its Adcom, the Executive Committee of VLSI Symposium and has been the TPC chair of ESSCIRC 2020 and 2021 in Grenoble. She has been for 10 years involved with ISSCC as RF subcommittee chair and then member of the Executive Committee. She is as well a founding member of the IEEE SSCS Women in Circuits group. Andreia has authored or co-authored 150+ technical papers and 14 book chapters, has co-edited the Springer book “The Fourth Terminal, Benefits of Body-Biasing Techniques for FDSOI Circuits and Systems” and has filed more than 25 patents. Andreia is a co-recipient of the ISSCC 2012 Jan Van Vessem Award for Outstanding European Paper, the ISSCC 2013 Jack Kilby Award for Outstanding Student Paper and the RFIC2021 Best Industry Paper Award. She is as well the winner of the 2012 STMicroelectronics Technology Council Innovation Prize, for having introduced on the company’s roadmap the integrated CMOS THz technology for imaging applications. Very recently, Andreia has been awarded an Honorary Doctorate from the University of Lund, Sweden, promotion of 2020.
Abstract： This talk will first present a very short overview of the major analog and RF technology features of the 28nm FDSOI planar CMOS technology. Then we will focus on the benefits of FD-SOI technology for analog/RF circuits with focus on IoT applications. Attendees will learn about design techniques that take full advantage of the unique capabilities of FD-SOI, including body biasing to efficiently modulate on the fly SoC solutions from high performance operation to energy efficiency mode. This further enhances the excellent analog/RF performances of these devices. The second part of the presentation will focus on novel design techniques that take full benefit of the new fourth transistor electrode (the body tie) and permit to get concurrent solutions that overcome the existing state of the art.
(More keynotes information to be released soon)