Prof. Albert Wang, University of California, Riverside, USA

K3-2: 9:45-10:30, Oct. 24, 2024, Thursday

Title: On-Chip ESD Protection: Methodologies, Challenges and Perspectives

Abstract:

No chip may be sold without ESD protection. On-chip ESD protection remains a major design challenge for ICs, especially for complex chips at advanced technology nodes, as well as for emerging heterogeneous integration (HI) technologies and integrated-systems-on-chiplets (SoIC). ESD protection design optimization, validation and prediction become very important to advanced ICs, which requires good ESD design methodologies. This paper reviews advances in on-chip ESD protection designs. Emerging ESD design challenges and future ESD protection perspectives will be highlighted.

Biography:

Prof. Albert Wang received the BS degree from Tsinghua University and the PhD degree from State University of New York at Buffalo. He is a Professor of Electrical and Computer Engineering at University of California, Riverside, USA. His research covers semiconductor devices, AMX/RF ICs, design-for-reliability for ICs, 3D heterogeneous integration, emerging devices and circuits, and LED visible light communications. He published two books and 320+ peer-reviewed papers, and holds 16 U.S. patents. His editorial board services include IEEE TCAS I, IEEE EDL, IEEE TCAS II, IEEE TED, IEEE JSSC, and IEEE TDMR. He is/was IEEE Distinguished Lecturer for IEEE EDS/CASS/SSCS. He was President of IEEE Electron Devices Society. His other committee services include the International Technology Roadmap for Semiconductor (ITRS), IEEE Heterogeneous Integration Roadmap (HIR), IEEE 5G Initiatives, IEEE Smart Lighting Project Roadmap and IEEE Fellow Committee. He was General Chair of IEEE EDTM2021 and IEEE RFIC2016. He was Program Director of National Science Foundation, USA. He was recipient IEEE J. J. Ebers Award and IEEE EDS Distinguished Service Award. Wang is a Fellow of National Academy of Inventors, an IEEE Fellow and an AAAS Fellow.