Hall 68，B1 Floor，
Nanjing Platinum Hanjue Hotel
9:00 – 10:30
T1-1 Energy/Data-Autonomous AIoT CMOS Integrated Platform Using Localized Energy/Data Generation and Consumption
Speaker：Prof. Kiichi Niitsu，Nagoya University，Japan
Abstract：This tutorial focuses on energy/data-autonomous AIoT CMOS integrated platform using localized energy/data generation and consumption. Guaranteeing stable energy is one of the most critical tasks for today’s AIoT development. Localized energy harvesting is promising approach for addressing this issue, but the new circuit techniques are required with taking characteristics of each energy sources into account. In addition to energy, it is better to manage the data locally in terms of energy efficiency. As a case study of this strategy, development of stand-alone continuous glucose monitoring contact lenses will be introduced. By employing glucose fuel cells and CMOS supply-sensing platform with wireless/LED-driving capability, localized energy/data generation and consumption has been achieved.
Bio：In 2010, he completed the doctoral program at Keio University Graduate School and became an Assistant Professor at the Graduate School of Engineering, Gunma University in the same year. From 2012, he was a Lecturer at the Graduate School of Engineering, Nagoya University. In 2013, served as a visiting researcher at Imperial College London. In 2015 - 2019, he served concurrently as Precursory Research for Embryonic Science and Technology (PRESTO) researcher, Japan Science and Technology Agency (JST). Since 2018, he is an Associate Professor at Nagoya University, Graduate School of Engineering. Since November 2020, he serves as PRESTO researcher (concurrently, IoT).
10:45 – 12:15
T1-2 Circuit and System-Level Considerations towards a scalable trapped ion quantum computer and quantum metrology applications
Speaker: Prof. Vadim Issakov, Braunschweig University of Technology, Germany
Abstract: This tutorial discusses in a systematic way the challenges and system-level aspects related to integrated circuits for miniaturization of a trapped ion quantum computer and systems for quantum metrology applications.
First, system level aspects and physics review of a trapped ion quantum computer operation is given. Particularly, near-field microwave quantum logic is described in detail (on example of Be+, Ca+ and Yb+ ions). Various parts of the system are presented including microwave power amplifiers with envelope shaping along with integrated direct digital synthesizers (DDS) to drive Mølmer–Sørensen gates or high-speed DACs controlling the shuttling motion of the ions to the registers on the chip.
The current state of the art electronic realization is shown using off-the-shelf equipment. Next, the potential of miniaturization and scalability of the trapped ion quantum computer by means of integration is visualized. The required system-on-chip is described in detail and specified to building blocks. The challenges related to achieving the electrical specifications (such as suppression of unwanted harmonics or port isolation) are discussed. Modelling results at cryogenic temperature of SiGe HBT and MOS transistors of 0.13 µm SiGe HBT BiCMOS technology are presented. The results of modelling are applied to design of the microwave sources for controlling the qubit states and the impact of modelling is shown. Finally, a system-on-chip for driving the trapped ions is discussed.
Another example of integrated circuit design for quantum application is shown for quantum metrology. A system-on-chip driving Josephson Arbitrary Waveform Synthesizer (JAWS) is presented. The highly integrated system comprising a PLL, memory and serdes, drives a 217 bit long-modulated sequence at a speed of 100 Gbps (with an on-chip generated clock of 100 GHz) onto a JAWS chip to create an extremely high purity flux quantized signal.
Finally, a vision on modelling and circuit design for circuits operating up to very high frequencies at cryogenic temperatures for quantum applications is given.
Bio: Vadim Issakov received the M.Sc. degree in microwave engineering from TU Munich in 2006 and the Ph.D. degree (summa cum laude) from the University of Paderborn, Germany, in 2010. In March 2010, he joined Infineon, Neubiberg, Germany. He worked with IMEC, Belgium and Intel Corporation, before he came back to Infineon in August 2015 as Lead Principal Engineer heading a research group working on pre-development of mm-wave radar and communication products. He was with the University of Magdeburg from September 2019 as a Full Professor, until he joined Braunschweig University of Technology, Germany as Full Professor and Head of Institute for CMOS Design in April 2021. His research activities focus on this domains design of integrated circuits for radar applications, biomedical and quantum computing applications. He has authored or coauthored more than 120 articles in international journals and conference proceedings, 11 patents, and has published a book on mm-wave circuits for radar applications. He received an Award for the Outstanding Dissertation from the VDE (German Association of Engineers) in Germany and the Best Dissertation Award from the University of Paderborn. His work has been recognized by the IEEE MTT Outstanding Young Engineer Award 2019.
13:30 – 15:00
T2-1 Impact and applications of device imperfectness in emerging computing technologies
Speaker: Prof. Zheng Chai，Xi'an Jiaotong University, China
Abstract: In-memory computing, stochastic computing, and neuromorphic computing are strong candidates for overcoming the big data challenge faced by future computing systems in the post-Moore's law era. The emerging memory devices, such as the non-volatile memristors and the volatile selectors, have demonstrated promising penitential in these emerging computing technologies. Despite their fast-speed, high scalability, simple structure and low power consumption, the intrinsic imperfectness in these devices, such as the noise and variability, are generally considered as undesirable. However, it is often overlooked that the imperfectness could play a role to enhance the performance of the emerging computing systems. In this paper we will first analyse the impact of random telegraph noise (RTN) in resistive-switching memory (RRAM) devices on in-memory computing. We will also utilize the switch-on variability of ovonic threshold switching (OTS) selectors for stochastic computing; Finally, we will investigate the application of 1/f noise in suppressing the overfitting issue in long short-term memory (LSTM) neuromorphic computing. This work provides useful information for the development of emerging computing technologies.
Bio: Zheng Chai received his B.S. and M.S. degrees in solid-state electronics & microelectronics from Xidian University in 2011 and 2014 respectively, and Ph.D degree in microelectronics from Liverpool John Moores University (LJMU) in 2017. From 2017 to 2020, he worked in the microelectronics characterization research group in LJMU as a post-doctoral researcher. During 2014-2019, he also worked in the memory device department (MDD) of the Interuniversity microelectronics centre (IMEC) under a collaboration research program focusing on the mechanism and reliability analysis of novel chalcogenide-based Ovonic threshold switching (OTS) selector devices. In 2020, he joined the School of Material Science and Engineering of Xi’an Jiaotong University as an associate professor. He is currently interested in the mechanism, reliability (semiconductor noise, defect characterization, etc.) and novel applications (in-memory computing, hardware security, etc.) of emerging memory devices including STT-MRAM, RRAM and OTS selectors. In the past 5 years, he has published more than 20 papers in international journals and premier conferences such as IEEE Electron Device Letters, IEEE Transactions on Electron Devices, IEEE International Electron Device Meeting (IEDM) and IEEE Symposium on VLSI Technology (VLSI).
15:00 – 16:30
T2-2 Photolithography, Process, Equipment, Material, Process Standards, and Future Outlook
Speaker: Prof. Qiang Wu, Fudan University, China
Abstract: Photolithography has been once of the key technical enablers for the fast development of the semiconductor integrated circuit industry. It started as contact-proximity image replication and has quickly evolved into the modern projection imaging based printing, which has the advantage of high fidelity, good positioning accuracy, high throughput, and relatively speaking low cost. In this tutorial, we will first provide a introduction of the basics of the photolithography, including a brief history, the standard 8-step processes, i.e., coating, baking, and exposure, etc., exposure equipment, photoresist material, photomask, computational algorithms, etc. Second, we will provide a review of the series of innovations that contribute to the advancement of the technology, i.e., the phase shifting mask, the chemically amplified photoresist material, polarized imaging, Extreme Ultra Violet (EUV) imaging, etc. Next, we will provide a result of our process performance study over the past 30 years from 0.25 mm technology node to the current 5 nm node, in which, we will reveal and explain the implicit standard for the major process window parameters, such as the Exposure Latitude (EL), Mask Error Factor (MEF), and Depth of Focus (DoF), etc. Lastly, we will provide an outlook for the future of photolithography.
Bio: Graduated in 1993 from Fudan University with B.S. and Ph.D. from Yale University in 1999, joint IBM Microelectronics as a lithography development staff engineer from 2000 till 2004, joint Huahong NEC as a section manager on lithography process development from 2004 till 2007, joint ASML as an equipment application manager from 2007-2010, joint SMIC as a department manager on lithography process development in 2010-2016 and SMIC ATD in 2016-2018. Joint Shanghai IC R&D Center in 2018-2021. Joint school of microelectronics Fudan University in 2021 as a professor. Has experience in photo process development from 0.25 nm to 7 nm, and has been granted 83 patents with 38 US patents and published more than 70 technical papers and a book in Chinese language titled “Photolithography process near the diffraction limit”. Has acted as the lithography chair for ISTC in 2007-2009 and lithography vice chair for CSTIC since 2010.
T2-3 Monolithic 3D integration for future optoelectronics
Speaker: Prof. Sanghyeon Kim, KAIST, Korea
Abstract: This tutorial reviews the history of 3D integration from the TSV (through Si via)-based approaches to monolithic 3D (M3D) integration. Regardless of the approaches, 3D integration provides lots of benefits such as reduced power consumption, improved speed/bandwidth, enhanced functionality, process flexibility, etc. This tutorial will discuss the impact of the 3D integration and how it will be implemented in future optoelectronic mixed-signal IC showing recent device demonstrations. Especially, some applications such as RF chips, image sensors, MicroLED displays, etc. will have advantages from 3D integration because they need high density (fill factor), new functionality/material integration, which Si cannot provide.
Bio: Prof. Sanghyeon Kim received his B.S., M.S., and Ph.D. degrees in electronic engineering from The University of Tokyo, Japan, in 2009, 2011, and 2014, respectively. After his Ph.D., he was with Korea Institute of Science and Technology (KIST), Korea in 2014 until he moved to Korea Advanced Institute of Science and Technology (KAIST), Korea in 2019. Before joining KAIST, he was a post-doc at imec, Belgium from 2017 to 2018. He is currently an associate professor with the school of electrical engineering, KAIST, Korea. His current research interests include Next-generation computing/communication devices, monolithic 3D integration, MicroLED, thin-film imager, and MID-IR photonics, etc.
More to come, stay tuned