International Conference on Solid-State and Integrated Circuit Technology


Nov. 32020  Tuesday


Wyndham Grand Plaza Royale Hotel

Kunming, China




Tutorial Sessions



Meeting Room 1,  6th Floor.,


9:00 – 10:30  


T-1 Electrostatic Discharge Design for Digital, Analog and Radio Frequency (RF) Applications


SpeakerDr. Steven Voldman , Comcast, USA



AbstractIn this short course, electrostatic discharge (ESD) principles, and design will be discussed for digital, analog, mixed signal, and radio frequency (RF) designs. This course will focus on how to layout and design circuits and full-chip to provide maximum ESD robustness for products to avoid ESD failures and provide maximum success in qualification and product release.  The course will also provide a clear distinction of ESD design practices in different chip applications.  Analog and RF design principles will be applied to ESD design to provide optimum solutions for the product types. Circuit solutions and ESD designs will be discussed and product floor planning and architecture. Additionally, the course will discuss layout and design for digital, analog and mixed signal architectures.  Examples and material as well as invention concepts will be drawn from the author’s books on ESD, EOS, and latchup. This course will differ from prior ESD courses with an emphasis on circuit design and layout.


BioDr. Steven H. Voldman is the first IEEE Fellow in the field of electrostatic discharge (ESD) for “Contributions in ESD protection in CMOS, Silicon On Insulator and Silicon Germanium Technology.”   He received his B.S. in Engineering Science from University of Buffalo (1979); a first M.S. EE (1981) from Massachusetts Institute of Technology (MIT); a second degree EE Degree (Engineer Degree) from MIT; a MS Engineering Physics (1986) and a Ph.D in electrical engineering (EE) (1991) from University of Vermont under IBM's Resident Study Fellow program.   In 2018, Dr. Voldman served as an International Visiting Scholar at Khon Kaen University in Khon Kaen, Thailand.


Dr. Voldman’s latest book is released in 2019, titled Electrostatic Discharge: From Electrical breakdown in Micro-gaps to Nanogenerators, and a second book Integrated Circuit Design for Radiation Environments.  In 2018, a new book titled From Invention and Patent and a contributor to the book Nanoelectronics: Nanowires, Molecular Electronics, and Nano-devices was released. Dr. Voldman  is an author of the first book series on ESD, EOS and latchup:  ESD: Physics and Devices, ESD: Circuits and Devices, 2nd Edition of ESD: Circuits and Devices, ESD: Radio Frequency (RF) Technology and Circuits, Latchup, ESD: Failure Mechanisms and Models,  ESD Design and Synthesis, ESD Basics: From Semiconductor Manufacturing to Product Use, and Electrical Overstress (EOS): Devices, Circuits and Systems, ESD: Analog Circuits and Design, ESD Testing: From Component to Systems,  as well as a contributor to the book Silicon Germanium: Technology, Modeling and Design and  In addition, the International Chinese editions of book ESD: Circuits and Devices,  ESD: Radio Frequency (RF) Technology and Circuits, and ESD Design and Synthesis  (2014) 


Voldman was a member of the semiconductor development of IBM, Qimonda, Intersil, Taiwan Semiconductor Manufacturing Corporation (TSMC), Samsung Electronics Corporation, and Silicon Space Technology / VORAGO Corporation.  His research and development includes soft error rate (SER), cosmic rays, gate induced drain leakage mechanisms, DRAM leakage, latchup, ESD and EOS.  He initiated a university lecture program which was established to bring  lectures and interaction to university faculty and students internationally; the program has reached over 45  universities in the Thailand, Malaysia, Singapore, United States, Korea, Taiwan, Philippines, India, Senegal, Swaziland, Zimbabwe, Nepal, and China.  Dr. Voldman has teaches short courses and tutorials on ESD, latchup, patenting, and invention.  Dr. Voldman was responsible for initiating the ESD Student Chapter charter, and worked with UESTC in establishment of the first  ESD Association student chapter.


He is a recipient of 263 issued US patents and has written over 150 technical papers in the area of ESD and CMOS latchup. Since 2007, he has served as an expert witness in patent litigation; and has also founded a limited liability corporation (LLC) consulting business supporting patents, patent writing and patent litigation.  In his LLC, S. Voldman served as an expert witness for cases on DRAM development, semiconductor development, integrated circuits, software, and electrostatic discharge.  He is presently writing patents for law firms and technology corporations.  Steven Voldman provides tutorials and lectures on inventions, innovations, and patents in Malaysia, Sri Lanka and the United States.





10:45 – 12:15


T-2 CMOS Transceiver Realizing Terahertz Wireless Communication, The Key Technology of Beyond 5G

Speaker Prof. Minoru Fujishima,

Graduate School of Advanced Sciences of Matter, Hiroshima University, Japan



Abstract: The 300 GHz band is a low frequency range of terahertz. Terahertz is an electromagnetic wave located between a radio wave and a light wave, and has a very high frequency band of the radio wave. Therefore, there is an advantage that a wide frequency band can be used for high-speed communication. As a result, if the terahertz communication is realized, it is possible to solve the problem that the speed of the wireless communication is significantly slower than the speed of the fiber-optic communication or the wired communication. At present, the communication infrastructure is constructed with optical fibers, but the era of the fiber-optic-speed network has spread to a place where only relatively low-speed wireless communication can link.


On the other hand, terahertz has a disadvantage that it is difficult to generate a high-output signal. In recent years, both device and circuit technologies have been improved and this problem is being solved. Silicon integrated circuits, especially complementary metal oxide semiconductor integrated circuits (CMOS), were considered unsuitable for terahertz communication because the high frequency performance of silicon transistors was inferior to that of compound semiconductor transistors. However, wireless circuits used in mass-produced mobile phones and personal computers (PCs) are currently made of inexpensive CMOS integrated circuits due to improvements in circuit and device technology. Advanced signal processing is essential for infrastructure devices that span satellites and the terminals connected to them. CMOS integrated circuits are important to realize terahertz communication and advanced signal processing on a single chip at low cost. We chose CMOS integrated circuits because we thought that we could overcome the performance of silicon transistors by devising the circuit. This tutorial introduces 300GHz band wireless communication technology using CMOS.


Bio: Minoru Fujishima received the B.E., M.E. and Ph.D degrees in Electronics Engineering from the University of Tokyo, Japan in 1988, 1990 and 1993, respectively. He joined faculty of the University of Tokyo in 1988 as a research associate, and was an associate professor of the School of Frontier Sciences, University of Tokyo since 1999. He was a visiting professor at the ESAT-MICAS laboratory, Katholieke, Universiteit Leuven, Belgium, from 1998 to 2000. Since 2009, he has been a professor of the Graduate School of Advanced Sciences of Matter, Hiroshima University.

He studied design and modeling of CMOS and BiCMOS circuits, nonlinear circuits, single-electron circuits, and quantum-computing circuits. His current research interests are in the designs of low-power millimeter- and short-millimeter-wave wireless CMOS circuits. He coauthored more than 50 journal papers and 120 conference papers. He served as a distinguished lecturer in IEEE solid-state circuits society from 2011 to 2012.





14:00 – 15:30


T-3 Fabrication and Applications of Bulk and SOI FinFETs


Speaker: Dr. Rita Rooyackers

ClaRoo, Leuven, Belgium



Abstract: FinFET based Multi-Gate (MuGFET) devices have been widely studied and have shown to be one of the most promising technology solutions that has the potential to meet the requirements for scaling CMOS into the 14nm technology node and beyond. The achieved enhanced channel conduction is due to contributions from both top and sidewalls of the fin. Therefore the effective width of a triple gate MuGFET is given by WEFF = n(WFIN + 2HFIN) , where n, WFIN and HFIN are the number, width and height of the fins, respectively. The ultimate current driving capability of the technology is determined by the minimum usable spacing (S2) between two adjacent fins.

In this talk we will address a number of integration challenges like the fin dimensions and gate patterning (control of the critical dimensions), the junction formation on fin-structures, the application of strain as a mobility booster … for both SOI and bulk finFETs.  In addition, it will be briefly demonstrated how fin-structures can be used to fabricate nanowires enabling to integrate gate all around devices improving the electrostatic channel control.


Bio: Rita Rooyackers received the degree in industrial chemistry from the Rega Institute for Medical Research, Katholieke Universiteit Leuven (KU Leuven), Leuven, Belgium, in 1975, where she followed the basics of VLSI processing of the PMMS program. From 1976 to 1984, she was with the ESAT Laboratory, KU Leuven, for silicon technology development. From 1984 to 2017, she was with imec, Leuven, Belgium where she was active  in the field  of process technology development and integration of advanced devices like FinFETs, TFETs and vetical and horizontal nanowires, both in silicon and III-V technologies . She is the co-author of about 150 publications in those fields





15:45 – 17:15


T-4 Physical Hardware Attacks with Machine Learning

Speaker: Prof. Bah-Hwee Gwee

NTU, Singapore



Abstract: Banking, defence applications and cryptosystems often demand security features, including cryptography, tamper resistance, stealth, and etc., by means of hardware approaches and/or software approaches to prevent data leakages. The hardware physical attacks or commonly known as side channel attacks have been employed to extract the secret keys of the encrypted algorithms implemented in hardware devices by analyzing their physical parameters such as power dissipation, electromagnetic interference and timing information. Altered functions or unauthorized modules may be added to the circuit design during the shipping and manufacturing process, bringing in security threats to the deployed systems. In this tutorial, we will discuss hardware physical attacks from both circuit/system and device levels, and present how machine learning techniques can be utilized. At the circuit/system level, we will first provide an overview of the different cryptography algorithms and present the side channel attacks, particularly the powerful Correlation Power Analysis (CPA) and Correlation Electromagnetic Analysis (CEMA) with a leakage model that can be used to reveal the secret keys of the cryptosystems. We will then discuss several countermeasure techniques and present how highly secured microchips can be designed based on these techniques. At the device level, we will provide an overview of manufactured IC circuit analysis through invasive IC delayering and imaging. We then present several machine learning techniques that can be efficiently applied to the retrieval of circuit contact points and connections for further netlist/functional analysis.


Bio: Dr Bah-Hwee Gwee received his B.Eng degree from University of Aberdeen, UK, in 1990.   He received his MEng and PhD degrees from Nanyang Technological University in 1992 and 1998 respectively.    He was an Assistant Professor of School of EEE, NTU from 1999 to 2005.   He is currently an Associate Professor in School of EEE, NTU.   He has worked on a number of research projects with research grant amounting to S$8m (~US$5.7m).    He was the principal investigator of the research projects from MoE Academic Research Tier-2 grant of S$1.3m (~US$860k), ASEAN-EU University Network Programme grant of €200k and the Defense Science Organization grant of S$3.25m (~US$2.32m).   He was also the Co-Principal Investigator of NTU-Panasonic research collaboration amounting to S$1m (~US$800k) and DARPA project of ~US$350k, Linkoping University – NTU joint research collaboration of S$660k (~US$400k), The Agency for Science, Technology and Research (A*STAR) – PSF research project of S$700k ((USD500k).   His research interests include low power asynchronous IC design, Class-D amplifiers, digital signal processing and soft computing.   He has published more than 100 technical papers, 6 patents (3 granted in USA) and started 2 Start-up Companies in 2005 and in 2020.


He was the Chairman of IEEE-Singapore Circuits and Systems Chapter in 2005, 2006, 2013 and 2016.   He is the Chairman of IEEE Circuits and Systems Society – DSPTC (2019-2020).   He was the General Co-Chair of IEEE DSP 2018 and IEEE SOCC 2019.   He was the organizing committee of the IEEE Bio-CAS 2004, IEEE APCCAS 2006 and the TPC Chair of International Symposium on Integrated Circuits (ISIC 2007, ISIC 2011 and ISIC 2016).   He has also served as Associate Editors of a number of journals, including IEEE Transactions of Circuits and Systems II – Brief Express (2010-2011, 2018-2019 and 2020-2021), IEEE Transactions of Circuits and Systems I – Regular Papers (2012-2013) and Journal of Circuits, Systems and Signal Processing (2007-2012). He was awarded Temasek Laboratories @ NTU Best Publication Award in 2012 and the Teaching Excellence Award (Year 3) in 2013. He was an IEEE Distinguished Lecture for Circuits and Systems Society in 2009-2010 and in 20172018. He was awarded the Singapore Defence Technology Prize in 2016.


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