ICSICT 2018 Tutorial Session

Date: Oct. 312018

Time: 9:00-10:30

Location: Room F+G, 3rd FL

Sheraton Huangdao HotelQingdaoChina

T-1 Development of Electrostatic Discharge Protection Solutions Based on Silicon Controlled Rectifier

Speaker: Prof. J. J. Liou, Zhengzhou University, China



AbstractElectrostatic discharge (ESD) is one of the most prevalent threats to the reliability of electronic components. It is an event in which a finite amount of charge is transferred from one object (i.e., human body) to the other (i.e., microchip). This process can result in a very high current passing through the microchip within a very short period of time, and more than 35% of single-event catastrophic damages can be attributed to such an event.  As such, designing robust on-chip ESD structures to protect microchips against ESD stress is a high priority in the semiconductor industry. The continuing scaling of CMOS technology makes the ESD-induced failures even more prominent, and one can predict with certainty that the availability of effective and robust ESD protection solutions will be a critical factor to the success of the deep sub-micron technology advancement. In fact, many semiconductor companies worldwide are having difficulties in meeting the increasingly stringent ESD protection requirements for various electronics applications.


There has been a wide spread use of integrated circuits in consumer applications. An example is the automotive electronics which are typically operated in a voltage range of 40-60 V. This relatively high-voltage operation imposes certain challenges to the design of ESD protection solutions embedded in the modern vehicles. On the other hand, due to the huge market of civil wireless communications, low-voltage integrated circuits are also in high demands. Effective ESD protection solutions for these high-speed circuits are typically required to operate within a very narrow ESD design window and with a minimal loading effect (i.e., high transparency), hence introducing a different set of challenges. Moreover, the continuing scaling of CMOS process toward the 10-nm node makes the design and realization of advanced ESD protection solutions even more demanding and difficult in the coming years.


This talk will present various effective ESD protection solutions for low- and high-voltage applications developed using a semiconductor device called silicon controlled rectifier. In addition, challenges and difficulties associated with designing ESD protection solutions in advanced CMOS process will also be discussed.   


Bio: Juin J. Liou received the B.S. (honors), M.S., and Ph.D. degrees in electrical engineering from the University of Florida, Gainesville, in 1982, 1983, and 1987, respectively. In 1987, he joined the Department of Electrical and Computer Engineering at the University of Central Florida (UCF), Orlando, Florida, where he held the positions of UCF Pegasus Professor and Lockheed Martin Chair Professor of Engineering. His current research interests are Micro/nanoelectronics computer-aided design, RF device modeling and simulation, and electrostatic discharge (ESD) protection design and simulation. Currently, he is the president of Emoat, LLC, a consulting firm which provides know-how and expertise on the design and characterization of ESD solutions. He also serves as a chair professor of Zhengzhou University, China and endowed professor of Zhejiang University, China.

       Dr. Liou holds 12 U.S. patents (1 more filed and pending), and has published 13 books, more than 290 journal papers (including 21 invited review articles), and more than 240 papers (including more than 110 keynote and invited papers) in international and national conference proceedings. He has been awarded more than $14.0 million of research contracts and grants from federal agencies (i.e., NSF, DARPA, Navy, Air Force, NASA, NIST), state government, and industry (i.e., Semiconductor Research Corp., Intel Corp., Intersil Corp., Lucent Technologies, Alcatel Space, Conexant Systems, Texas Instruments, Fairchild Semiconductor, National Semiconductor, Analog Devices, Maxim Integrated Systems, Allegro Microsystems, RF Micro Device, Lockheed Martin), and has held consulting positions with research laboratories and companies in the United States, China, Japan, Taiwan, and Singapore.  In addition, Dr. Liou has served as a technical reviewer for various journals and publishers, general chair or technical program chair for a large number of international conferences, regional editor (in USA, Canada and South America) of the Microelectronics Reliability journal, and guest editor of 7 special issues in the IEEE Journal of Emerging and Selected Topics in Circuits and Systems, Microelectronics Reliability, Solid-State Electronics, World Scientific Journal, and International Journal of Antennas and Propagation.

Dr. Liou received ten different awards on excellence in teaching and research from the University of Central Florida (UCF) and six different awards from the IEEE. Among them, he was awarded the UCF Pegasus Distinguished Professor (2009) – the highest honor bestowed to a faculty member at UCF, UCF Distinguished Researcher Award (four times: 1992, 1998, 2002, 2009), UCF Research Incentive Award (four times: 2000, 2005, 2010, 2015), IEEE Joseph M. Biedenbach Outstanding Engineering Educator Award in 2004 for exemplary engineering teaching, research, and international collaboration, and IEEE Electron Devices Society Education Award in 2014 for promoting and inspiring global education and learning in the field of electron devices. His other honors are Fellow of IEEE, Fellow of IET, Fellow of Singapore Institute of Manufacturing Technology, Fellow of UCF-Analog Devices, Distinguished Lecturer of IEEE Electron Device Society (EDS), and Distinguished Lecturer of National Science Council. He holds several honorary professorships, including the Chang Jiang Scholar Endowed Professor of Ministry of Education, China – the highest honorary professorship in China, NSVL Distinguished Professor of National Semiconductor Corp., USA, International Honorary Chair Professor of National Taipei University of Technology, Taiwan, Honorary Endowed Professor of National Taiwan University of Science and Technology, Taiwan, Chang Gung Endowed Professor of Chang Gung University, Taiwan, Feng Chia Chair Professor of Feng Chia University, Taiwan, Chunhui Eminent Scholar of Peking University, China, Cao Guang-Biao Endowed Professor of Zhejiang University, China, Honorary Professor of Xidian University, China, Consultant Professor of Huazhong University of Science and Technology, China, and Courtesy Professor of Shanghai Jiao Tong University, China. Dr. Liou was a recipient of U.S. Air Force Fellowship Award and National University Singapore Fellowship Award.

       Dr. Liou has served as the IEEE EDS Vice-President of Regions/Chapters, IEEE EDS Treasurer, IEEE EDS Finance Committee Chair, Member of IEEE EDS Board of Governors, and Member of IEEE EDS Educational Activities Committee.



Time: 10:45-12:15

T-2 General Design Flow of a High Performance SAR-Type ADCs  

Speaker:  Dr. Yan Zhu, University of Macao, China




SAR ADCs achieve excellent power efficiency and friendliness to technology scaling thanks to the simple and highly-digitized architecture, while its conversion speed is limited by its sequential conversion. Hybrid SAR-type ADC takes the design advantages of multi conventional architectures to optimize the conversion speed, resolution and power dissipation. This talk introduce a general design flow of a SAR-SAR sub-ranging ADC, covering the design considerations of the basic building blocks, such as comparator, DAC and logic. A design example is based on required noise budge for target ADC specification. 


Bio: Yan Zhu received the B.Sc. degree in electrical engineering and automation from Shanghai University, Shanghai, China, in 2006, and the M.Sc. and Ph.D. degrees in electrical and electronics engineering from the University of Macau Macao, China, in 2009 and 2011, respectively. She is now an assistant professor with the State Key Laboratory of Analog and Mixed-Signal VLSI, University of Macau, Macao, China. She received Best Paper award in ESSCIRC 2014, the Student Design Contest award in A-SSCC 2011, the Chipidea Microelectronics Prize and Macao Scientific and Technological R&D Awards in 2012, 2014 and 2016 for outstanding Academic and Research achievements in Microelectronics. She has published more than 50 technical journals and conference papers in her field of interests, and holds 3 US patents. Her research interests include low-power and wideband high-speed Nyquist A/D converters as well as digitally assisted data converter designs.


Time: 14:00-15:30

T-3  2D Electronics - Motivation, Prospects, and Challenges                   

SpeakerDr. Frank Schwierz Technische Universität (TU)

Ilmenau, Germany



AbstractDuring the past decade, 2D (two-dimensional) materials have attracted enormous attention. The rise of these materials began in 2004 with the pioneering work on graphene done at Manchester University and Georgia Tech. Particularly the observed high carrier mobilities raised early expectations that graphene could be the perfect electronic material. It soon became clear, however, that due its zero bandgap graphene is not suitable for transistors. On the other hand, researchers have extended their work to 2D materials beyond graphene and the number of such materials under investigation is continuously rising. Many of them possess sizeable bandgaps and therefore are potentially useful for transistors. Indeed, the progress in the field of 2D transistors has been rapid and experimental MOSFETs using a variety of different semiconducting 2D channel materials have been reported. A recent achievement was the demonstration of a well-performing 1-nm gate MoS 2 MOSFET in 2016. Moreover, currently 2D devices beyond transistors, such as 2D sensors and 2D memristors, attract considerable attraction.

In the present lecture, the most important classes of 2D materials are introduced and the potential of 2D transistors is assessed as realistically as possible. To this end, we examine two material properties – bandgap and mobility – in detail and discuss the mobility-bandgap tradeoff. The state of the art of 2D transistors is reviewed and their performance is compared to that of competing conventional transistors. We show that due to the rather conservative CMOS scaling scenario currently favored by the industry and set out in the 2015 ITRS (compared to the more aggressive scenarios of the previous ITRS editions), in the near- to-medium term the prospects of 2D materials in mainstream CMOS are rather gloomy. Regarding beyond-CMOS applications, on the other hand, the situation looks different. We show that 2D materials represent an interesting option for flexible electronics, sensors, and memristors. Current research in these areas is reviewed and key achievements are highlighted. We show that the work on 2D flexible electronics and 2D sensors is already well advanced while research on 2D memristors has just begun.


BioFrank Schwierz received the Dr.-Ing. and Dr. habil. degrees from Technische Universität (TU) Ilmenau, Germany, in 1986 and 2003, respectively. Presently he serves as Privatdozent at TU Ilmenau and is Head of the RF & Nano Device Research Group. His research is focused on novel device and material concepts for electronics and high-performance radio frequency transistors. At present he is particularly interested in two-dimensional electronic materials and devices. Dr. Schwierz is conducting research projects funded by the European Community, German government agencies, and the industry. Together with partners from academia and industry he was involved in the development of the fastest Si-based transistors worldwide in the late 1990s, of Europe's smallest MOSFETs in the early 2000s, as well as of the fastest GaN HEMTs on Si and the fastest GaN tri-gate HEMTs worldwide in the 2010s. His recent work on two- dimensional materials made a major contribution to the current understanding of the merits and drawbacks of graphene transistors. Dr. Schwierz has published more than 265 journal and conference papers including over 45 invited papers. He is author of the books Modern Microwave Transistors – Theory, Design, and Performance (J. Wiley & Sons 2003) and Nanometer CMOS (Pan Stanford Publishing 2010) and editor of the book Two-Dimensional Electronics – Prospects and Challenges (MDPI 2016). Dr. Schwierz is Senior Member of the IEEE. He serves as a Distinguished Lecturer of the IEEE Electron Devices Society and as an editor of the IEEE Transactions on Electron Devices. Moreover, he has been one of the key contributors to the Emerging Research Devices Technology Working Groups of the 2013 and 2015 ITRS editions and is now involved in the elaboration of the new Heterogeneous Integration Roadmap.


Time: 15:45-17:15

T-4  Interconnect Technologies for Post-Moore Era

Speaker: Prof. Mansun Chan, Hong Kong University of Science & Technology



AbstractThe scaling of CMOS has encountered many hurdles in the sub-10nm technology nodes as we are approaching the end of the Moore’s Law.  The performance limitations have shifted to the interconnect technology to reduce the metal wire resistance as well as the k-value of the interlayer dielectrics.  The popular interconnect materials such as copper and tungsten have been found to be insufficient due to increasing resistivity with dimension scaling and electromigration concern under high current density.  And using porous structures to form the interlayer dielectrics is subjected to the weakening of the mechanical strength of the dielectric film. New materials such as carbon nanotube (CNT) and graphene have been extensively studied to extend the scaling roadmap for interconnects. However, many barriers have to be overcome before these materials can enter mainstream manufacturing.  In this presentation, I am going to present some of the recent progresses in using CNT as a contact plug as well as an agent to form very low k-value interlayer dielectrics. 


BioProf. Mansun Chan received his Ph.D degree from the University of California at Berkeley. During his undergraduate study, he has been working with Rockwell International Laboratory on Heterojunction Bipolar Transistor (HBT) modeling, where he developed the self-heating SPICE model for HBT. His research at Berkeley covered a broad area in silicon devices ranging from process development to device design, characterization, and modeling. A major part of his work was on the development of record-breaking Silicon-On-Insulator (SOI) technologies. Dr. Chan has also maintained a strong interest in device modeling and circuit simulation. He is one of the major contributors to the unified BSIM model for SPICE, which has been accepted by most US companies and the Compact Model Council (CMC) as the first industrial standard MOSFET model. He joined the ECE faculty at Hong Kong University of Science and Technology after graduation. His research interests include nano-device technologies, 2-D material and technology, 3-D stacked circuit, Circuit simulation methodology, Device Modeling and Bioelectronic technology. Between July 2001 and December 2002, he was a Visiting Professor at University of California at Berkeley and the Co-director of the BSIM program. He is currently a Distinguished Lecturer and a Fellow of IEEE.



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